A first-in first-out (FIFO) buffer system can be implemented using single-port memory or two-port (or dual-port) memory. While a two-port memory allows multiple reads or writes to occur concurrently, it may be impractical to implement two-port memory due to its complexity or for other reasons. In situations whereby implementation of a two-port memory is difficult, designers have implemented single-port memory in a manner that mimics the behavior of a two-port memory by clocking the single-port memory at twice the frequency of a FIFO interface associated with the single-port memory. Conventional FIFO buffer systems, whether using two-port memory or over-clocked single-port memory, typically are subject to a delay of at least one clock cycle from when a read address is clocked in a memory to when the data is provided out of the memory, thereby inhibiting the throughput of the FIFO buffer.